/*
**************************************************************************************************************
File:         top.sv
Description:  Transactor for Veloce
Author     :  Aditya Joshi, Rohit Kulkarni
**************************************************************************************************************
*/

import params_pkg::*;

module top();
  
  //clk generation logic 

	logic CK,rst;
	reg fetch_next;
	//tbx clkgen
	initial
	begin
        CK=0;
        forever #10 CK=~CK;
	end

	//tbx clkgen
	initial 
	begin
		rst =1;
		#30 rst=0;
	end
	
	// DUT signals
	//reg command; 
  //reg [LOGICAL_ADDR_WIDTH-1:0] address;
  reg start;
  wire done;
  reg OP;
  reg [LOGICAL_ADDR_WIDTH-1:0] ADDR;
  
  // instantiating DUTs
  DDR_bus bus(.*);                                               //instantiate a DDR3 bus
  
  controller  DDR_controller(.IF(bus.memory_controller), .*);    //will use the mem_cntrl modport view

  DDR_memory  DDR_MEMORY(.IF(bus.memory_stub), .*);               //will use the mem_stub modport view
  
  //Input Pipe Instantiation 

	scemi_input_pipe #(.BYTES_PER_ELEMENT(packet_size_in_bytes),
                   .PAYLOAD_MAX_ELEMENTS(packet_size_in_bytes),
                   .BUFFER_MAX_ELEMENTS(100)
                   ) inputpipe(CK);
				   
	//Output Pipe Instantiation 

	/*scemi_output_pipe #(.BYTES_PER_ELEMENT(packet_size_in_bytes),
					   .PAYLOAD_MAX_ELEMENTS(packet_size_in_bytes),
					   .BUFFER_MAX_ELEMENTS(10)
					   ) outputpipe(CK);*/
  
  //XRTL FSM to obtain operands from the HVL side
	reg [(packet_size_in_bytes*8)-1:0] input_packet;
	bit eom=0;
	reg [7:0] ne_valid=0;
	reg issued;

	always@(posedge CK)
	begin
        
        if(rst)
        begin
     	    //command <= 0; 
          //address <= 0;
          start <= 0;
          OP <= 0;
          ADDR <= 0;
          fetch_next <= 1;     
        end
        else 
        if(fetch_next)
        begin
                //if(!issued)
                  begin
                    //outputpipe.send(1,done,1);                    
                    fetch_next <= 0;
                    inputpipe.receive(packet_size_in_bytes,ne_valid,input_packet,eom);
                    OP <= input_packet[39:32];
                    ADDR <= input_packet[31:0];
                    //issued <=1;
                    start <= 1;
                 end
                
            end
        //else
      else if(done)
          fetch_next <= 1;     
        
	end

	
endmodule
